1. Field of the Invention
The present invention relates to a semiconductor device, its production method and a semiconductor substrate structure of the device, and more particularly to: a semiconductor device constructed of an HEMT(High Electron Mobility Transistor), wherein a heterojunction is formed between adjacent compound semiconductor layers; a production method of the semiconductor device; and, a semiconductor substrate structure of the device.
2. Description of the Related Art
The HEMT, which is well known as a kind of FET(Field Effect Transistor), is not only capable of performing a high speed operation owing to the advantage of a so-called xe2x80x9chigh electron mobilityxe2x80x9d thereof, but also capable of operating in a superhigh frequency band, for example such as a microwave band and the like to output a large power with high efficiency. Consequently, the HEMT is widely used as a power transistor for use in a transmitter""s output unit and the like mounted on a satellite communication instruments and the like.
FIG. 12 is a cross-sectional view of a first conventional semiconductor device constructed of the HEMT described above, illustrating a structure of the device. In this first conventional device, for example, as showning FIG. 12, an undoped InGaAs (indium gallium arsenide) layer 103 serving as a channel layer is formed on a semi-insulating undoped GaAs (gallium arsenide) substrate 101 through a buffer layer 102, wherein the buffer layer 102 is formed of a GaAs layer or the like. Further formed on this undoped InGaAs layer 103 is an n-type AlGaAs layer 104 which serves as a carrier supply layer. Formed between the undoped InGaAs layer 103 and the n-type AlGaAs layer 104 is a heterojunction.
A gate electrode 105 which is made of, for example such as WSi (tungsten silicide) is formed in a central portion of the n-type AlGaAs (carrier supply) layer 104 to form a Schottky junction therein. Formed opposite sides of the gate electrode 105 are: a source contact layer 106 formed of, for example such as an n-type GaAs layer; and, a drain contact layer 107 formed of, for example such as an n-type GaAs layer. A source electrode 108 and a drain electrode 109 are formed in the source contact layer 106 and the drain contact layer 107, respectively. An oxide film 110 is formed in a recess portion formed between the gate electrode 105 and each of the source contact layer 106 and the drain contact layer 107, so that the gate electrode 105 is spaced apart from each of the source contact layer. 106 and the drain contact layer 107 by a distance corresponding to a film thickness of the oxide film 110.
In the above structure shown in FIG. 12, carriers are supplied from the n-type AlGaAs layer 104 to a surface of the undoped InGaAs layer 103 to form a two-dimensional electron layer (hereinafter referred to as the two-dimensional electron gas layer) 112. Electrons in this two-dimensional electron gas layer 112 produce a tunnel current. This tunnel current flows across the n-type AlGaAs layer 104 serving as a carrier supply layer, which makes it possible for the electrons to move between the source electrode 108 and the drain electrode 109, and thereby producing a drain current for supporting in operation the FET. Here, an electron density of the two-dimensional electron gas layer 112 is determined by both of a film thickness and an impurity concentration (hereinafter referred to simply as the concentration) of the n-type AlGaAs layer 104 serving as a carrier supply layer.
By the way, in order to improve the performance of the FET, it is necessary to reduce in level a parasitic resistance appearing in a channel between: the gate electrode 105; and, the source electrode 108 or the drain electrode 109. In order to reduce such parasitic resistance, it is indispensable to increase the concentration of the n-type AlGaAs layer 104 which serves as a carrier supply layer located directly below the gate electrode 105. On the other hand, when the concentration of the n-type AlGaAs layer 104 is increased, a so-called Schottky leak current (hereinafter referred to as the leak current) disadvantageously increases in a condition in which an effective gate breakdown strength disadvantageously decreases. Consequently, with respect to the concentration of the n-type AlGaAs layer 104 serving as a carrier supply layer, the trade-off in efforts to reduce the parasitic resistance is each of the increase of the leak current and the decrease of the gate breakdown strength.
Such trade-off problem mentioned above is solved by a second conventional semiconductor device disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 4-340234. In the second conventional semiconductor device, as shown in FIG. 13: a first high concentration n-type AlGaAs layer 113 is formed on. the undoped InGaAs layer 103 to reduce the parasitic resistance, wherein the undoped InGaAs layer 103 serves as a channel layer; and, a second low concentration n-type AlGaAs layer 114 is formed directly under the gate electrode 105 to reduce the leak current and increase the gate breakdown strength, whereby the second low concentration n-type AlGaAs layer 114 is piled on the first high concentration n-type AlGaAs layer 113 to form a double layer portion of a structure shown in FIG. 13.
Further, in this structure of FIG. 13, in order to effectively reduce the parasitic resistance, it is necessary to reduce the dimensions of each of the recess portions defined between the gate electrode 105 and each of the source contact layer 106 and the drain contact layer 107. Consequently, in the second conventional semiconductor device shown in FIG. 13, the gate electrode 105 is formed self-alignedly with the recess""s pattern of the source contact layer 106.
However, since the degree of reduction of the parasitic resistance achieved in the above is not sufficient, it is necessary to further reduce the parasitic resistance. In order to further reduce the parasitic resistance, it is considered to be effective that the n-type AlGaAs layer 114 serving as a second carrier supply layer has its impurity concentration partially increased to partially increase the concentration of the second carrier supply layer in the recess portion.
However, as is clear from the structure shown in FIG. 3, all the n-type AlGaAs layer 114 serving as the second carrier supply layer including the above recess portion is so formed as to have the same concentration. As a result, it is not possible for the structure of FIG. 3 to have only the recess portion thereof partially increased in impurity concentration. Consequently, when the second carrier layer is increased in impurity concentration to reduce the parasitic resistance in level, a portion directly under the gate electrode 105 is also increased in its impurity concentration together with the recess portion. This results in both the increase of the leak current and the reduction of the gate breakdown strength, as already described above.
A third conventional semiconductor device (shown in FIG. 14) is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 4-125939, in which an undoped AlGaAs layer corresponding to the n-type AlGaAs layer 114 serving as the second carrier supply layer shown in FIG. 13 is selectively formed only in a position directly under the gate electrode 105. In this third conventional semiconductor device, as shown in FIG. 14, an n-type AlGaAs layer 131 corresponding to a first carrier supply layer is formed on an undoped GaAs layer 123 serving as a channel layer. Further formed on this n-type AlGaAs layer 131 by a selective deposition process is an undoped AlGaAs layer 132 corresponding to the second carrier supply layer. Formed on this undoped AlGaAs layer 132 thus selectively deposited is the gate electrode 105. The third conventional semiconductor device, which is shown in FIG. 14 and has the above construction, is capable of effectively decreasing the parasitic resistance without increasing the leak current and without decreasing the gate breakdown strength.
On the other hand, a problem to be solved by the present invention is as follows: namely, In the third conventional semiconductor device disclosed in the Japanese Patent Application Laid-Open No. Hei 4-125939, as shown in FIG. 14, since the undoped AlGaAs layer 132 is formed directly under the gate electrode 105 by the selective deposition process, it is difficult to selectively deposit the undoped AlGaAs layer 132 with sufficient reproducibility, which increases the manufacturing cost of the third conventional semiconductor device.
In other words, in forming the undoped AlGaAs layer 132 by such selective deposition process of the Japanese Patent Application Laid-Open No. Hei 4-125939 during the production of the third conventional semiconductor device, it is difficult to establish optimum deposition conditions for forming the undoped AlGaAs layer 132. Due to this, the undoped AlGaAs layer 132 thus deposited tends to contain an abnormal deposition portion in its crystalline structure. Consequently, in order to form the layer 132 with sufficient reproducibility by removing the above-mentioned abnormal deposition portion from its crystalline structure, it is necessary to use an expensive special deposition technique, which increases the manufacturing cost of the third conventional semiconductor device.
In view of the above, it is an object of the present invention to provide a semiconductor device, its production method and a semiconductor substrate structure of the device, and more particularly to provide: a semiconductor device constructed of an HEMT(High Electron Mobility Transistor), wherein a heterojunction is formed between adjacent compound semiconductor layers; a production method of the semiconductor device; and, a semiconductor substrate structure of the device, without using any expensive special deposition technique increasing the manufacturing cost of the semiconductor device, wherein the semiconductor device of the present invention is capable of reducing its parasitic resistance without increasing a leak current thereof and also without decreasing a gate breakdown strength thereof.
According to a first aspect of the present invention, there is provided:
in a semiconductor device provided with a compound semiconductor substrate on which an undoped compound semiconductor layer serving as a channel layer is formed, wherein a plurality of n-type compound semiconductor layers are successively formed and piled up on the channel layer to form a carrier supply layer, the improvement wherein:
the carrier supply layer is constructed of a first, a second and a third n-type compound semiconductor layer;
the second n-type compound semiconductor layer is the lowest in impurity concentration among the first, the second and the third n-type compound semiconductor layer; and
a gate electrode is formed so as to be encircled with the third n-type compound semiconductor layer, and to have a Schottky junction formed in the second n-type compound semiconductor layer.
Also, according to a second aspect of the present invention, there is provided:
in a semiconductor device provided with a compound semiconductor substrate on which an undoped compound semiconductor layer serving as a channel layer is formed, wherein a plurality of n-type compound semiconductor layers are successively formed and piled up on the channel layer to form a carrier supply layer, the improvement wherein:
the carrier supply layer is constructed of a first, a second and a third n-type compound semiconductor layer;
the second n-type compound semiconductor layer is the lowest in impurity concentration among the first, the second and the third n-type compound semiconductor layer;
an etch stop layer is formed on the third n-type compound semiconductor layer through a film thickness compensating layer; and
a gate electrode is formed so as to have a Schottky junction formed in the second n-type compound semiconductor layer, wherein the gate electrode is encircled with at least both of the third n-type compound semiconductor layer and the film thickness compensating layer.
In the foregoing first and second aspects, a preferable mode is one wherein the undoped compound semiconductor layer serving as the channel layer is constructed of an InGaAs layer.
Further, a preferable mode is one wherein each of the first, the second and the third n-type compound semiconductor layer forming the carrier supply layer is constructed of an n-type AlGaAs layer.
Still further, a preferable mode is one wherein the film thickness compensating layer is constructed of a high resistance GaAs layer.
A preferable mode is one wherein the etch stop layer is made of the same material as that of the third n-type compound semiconductor layer.
Further, a preferable mode is one wherein each of a source contact layer and a drain contact layer is constructed of an n-type GaAs layer on the third n-type compound semiconductor layer in each of opposite sides of the gate electrode so as to be spaced apart from the gate electrode; and, an insulation film is formed between: each of the source contact layer and the drain contact layer; and, the gate electrode.
Still further, a preferable mode is one wherein the third n-type compound semiconductor layer or the etch stop layer has a film thickness substantially equal to that of a corresponding preform of the third n-type compound semiconductor layer or of the etch stop layer, wherein an exposed portion of the preform has been already removed through a series of etching processes prior to the formation of the gate electrode.
Also, according to a third aspect of the present invention, there is provided:
a production method of a semiconductor device including the steps of:
a channel layer forming step for forming a channel layer on a compound semiconductor substrate through a buffer layer, wherein the channel layer is constructed of an undoped InGaAs layer;
a carrier supply layer forming step for forming a carrier supply layer by successively forming and piling up a first, a second and a third n-type AlGaAs layer on the channel layer in this order to form the carrier supply layer, wherein the second n-type AlGaAs layer is the lowest in impurity concentration among the first, the second and the third n-type AlGaAs layer;
a contact layer forming step for forming a contact layer on the carrier supply layer, wherein the contact layer is constructed of an n-type GaAs layer;
a contact layer dividing step for dividing the contact layer into a source contact layer and a drain contact layer by forming a space portion therebetween, wherein the space portion is formed by selectively etching the contact layer using the third n-type AlGaAs layer of the carrier supply layer as an etch stop layer; and
a carrier supply layer selective removing step for selectively removing both an insulation film of the space portion and the third n-type AlGaAs layer of the carrier supply layer by an anisotropic etching process, wherein the insulation film is formed over the entire surface of the semiconductor substrate including the space portion, and the third n-type AlGaAs layer to be selectively removed is located directly under the insulation film of the space portion.
Also, according to a fourth aspect of the present invention, there is provided:
a production method of a semiconductor device including the steps of:
a channel layer forming step for forming a channel layer on a compound semiconductor substrate through a buffer layer, wherein the channel layer is constructed of an undoped InGaAs layer;
a carrier supply layer forming step for forming a carrier supply layer by successively forming and piling up a first, a second and a third n-type AlGaAs layer on the channel layer in this order to form the carrier supply layer, wherein the second n-type AlGaAs layer is the lowest in impurity concentration among the first, the second and the third n-type AlGaAs layer;
an etch stop layer forming step for forming an etch stop layer on the carrier supply layer through a film thickness compensating layer;
a contact layer forming step for forming a contact layer on the etch stop layer, wherein the contact layer is constructed of an n-type GaAs layer;
a contact layer dividing step for dividing the contact layer into a source contact layer and a drain contact layer by forming a space portion therebetween, wherein the space portion is formed by selectively etching the contact layer using the etch stop layer;
an etch stop layer selective removing step for selectively removing both an insulation film of the space portion and the etch stop layer by an anisotropic etching process, wherein the insulation film is formed over the entire surface of the semiconductor substrate including the space portion, and the etch stop layer to be selectively removed is located directly under the insulation film of the space portion; and
a carrier supply layer selective removing step for selectively removing both the film thickness compensating layer of the space portion and the third n-type AlGaAs layer of the carrier supply layer, wherein the third n-type AlGaAs layer to be selectively removed is located directly under the film thickness compensating layer.
A preferable mode is one wherein the film thickness compensating layer is constructed of a high resistance GaAs layer; and, the etch stop layer is constructed of an n-type GaAs layer.
Further, a preferable mode is one wherein the production method further includes a gate electrode forming step for forming a gate electrode in a manner such that a Schottky junction is formed in the second n-type AlGaAs layer.
Also, according to a fifth aspect of the present invention, there is provided:
a semiconductor substrate structure including:
an undoped InGaAs layer formed on a compound semiconductor substrate through a buffer layer, wherein the undoped InGaAs layer serves as a channel layer;
a carrier supply layer constructed of a first, a second and a third n-type AlGaAs layer which are successively piled up on the undoped InGaAs layer in this order to form the carrier supply layer, wherein the second n-type AlGaAs layer is the lowest in impurity concentration among the first, the second and the third n-type AlGaAs layer; and
a contact layer formed on the third n-type AlGaAs layer, wherein the contact layer is constructed of an n-type GaAs layer.
In the foregoing fifth aspect, a preferable mode is one wherein an etch stop layer constructed of an n-type AlGaAs layer is formed on the third n-type AlGaAs layer through a film thickness compensating layer, wherein the film thickness compensating layer is constructed of a high resistance GaAs layer.
With the above configurations, the undoped compound semiconductor layer serving as the channel layer is formed; successively formed and piled up on this undoped compound semiconductor layer are the first, the second and the third n-type compound semiconductor layer in this order to form the carrier supply layer in which the second n-type compound semiconductor layer is the lowest in impurity concentration among the first, the second and the third n-type compound semiconductor layer; the gate electrode is formed in a manner such that the Schottky junction is formed in the second n-type compound semiconductor layer; and, the third n-type compound semiconductor layer is formed so as to encircle the gate electrode.
Consequently, in a position directly under the gate electrode, there is no layer high in impurity concentration. Further, with the above fifth aspect, it is possible to integrally form a plurality of necessary compound semiconductor layers in producing the semiconductor device constructed of the heterojunction FET.
As a result, it is possible for the present invention to produce the compound semiconductor materials necessary for production of the semiconductor device of the present invention, at a low cost.
Further, without using any expensive special technique, the present invention is capable of reducing the parasitic resistance without increasing the leak current and without decreasing the gate breakdown strength in operation.